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| c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . l o w d r o p o u t l i n e a r r e g u l a t o r c o n t r o l l e r f e a t u r e s g e n e r a l d e s c r i p t i o n a p p l i c a t i o n s note book pc applications motherboard applications s i m p l i f i e d a p p l i c a t i o n c i r c u i t wide supply voltage range from 4.5 to 13.5v high output accuracy over operating temperature and loading ranges fast transient response power-on-reset monitoring on vcc internal soft-start function low shutdown current: < 5 m a enable control function under-voltage protection power-ok output with a delay time four versions of ic available: - apl5610: v ref =0.8v, uvp activated after v out is ready - apl5610a: v ref =0.8v, uvp activated after v cc is supplied - apl5610b: v ref =0.5v, uvp activated after v out is ready - apl5610c: v ref =0.5v, uvp activated after v cc is supplied sot-23-6 package lead free and green devices available (rohs compliant) p i n c o n f i g u r a t i o n - the apl5610 serise is a low dropout linear regulator controller. the apl5610 serise could drive an external n-channel mosfet and provides an adjustable output by using an external resistive divider. the apl5610 serise integrates various functions. for example, a power-on-reset (por) circuit monitors vcc supply voltage to prevent wrong operations; the function of under-voltage protection (uvp) protects the device from short circuit condition. a pok indicates that the output status with time delay which is set internally. it can con- trol other converter for power sequence. moreover, the apl5610 serise can be enabled by other power system; namely, holding the en above 1.6v enables output and pulling the en under 0.4 disables output. the apl5610 serise is available in a sot-23-6 package. apl5610/a/b/c sot-23-6 (top view) 4 pok 6 vcc gnd 2 5 drv fb 3 en 1 v cc v in en drv gnd apl5610 apl5610a apl5610b apl5610c pok fb v out vcc on off en pok
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 2 symbol parameter rating unit v cc vcc input voltage (vcc to gnd) - 0.3 to 15 v en, pok, to gnd voltage - 0.3 to 7 v v fb fb to gnd voltage - 0.3 to 7 v v drv drv to gnd voltage - 0.3 to v cc +0.3 v t j maximum junction temperature 150 o c t stg storage temperat ure - 65 to 150 o c t sdr maximum lead soldering temperature , 10 seconds 26 0 o c symbol parameter typical value unit q ja junction - to - ambient resistance in free a ir (note 2) sot - 23 - 6 250 o c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) t h e r m a l c h a r a c t e r i s t i c o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . n o t e 1 : s t r e s s e s b e y o n d t h o s e l i s t e d u n d e r " a b s o l u t e m a x i m u m r a t i n g s " m a y c a u s e p e r m a n e n t d a m a g e t o t h e d e v i c e . t h e s e a r e s t r e s s r a t i n g s o n l y a n d f u n c t i o n a l o p e r a t i o n o f t h e d e v i c e a t t h e s e o r a n y o t h e r c o n d i t i o n s b e y o n d t h o s e i n d i c a t e d u n d e r " r e c o m - m e n d e d o p e r a t i n g c o n d i t i o n s " i s n o t i m p l i e d . e x p o s u r e t o a b s o l u t e m a x i m u m r a t i n g c o n d i t i o n s f o r e x t e n d e d p e r i o d s m a y a f f e c t d e v i c e r e l i a b i l i t y apl5610 apl5610a apl5610b apl5610c package code c : sot-23-6 operating ambient temperature range i : -40 to 85 o c handling code tr : tape & reel assembly material g : halogen and lead free device handling code temperature range package code assembly material apl 5610 c: l10x x - date code apl 5610a c: la0x x - date code apl 5610b c: lb0x x - date code apl 5610c c: lc0x x - date code c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 3 r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) symbol parameter range unit v cc vcc input voltage (vcc to gnd) 4.5 to 13.5 v v en en to gnd voltage 0 t o 5.5 v v out vout output voltage (note4) 0.8/0.5 ~ v in - v drop v t a ambient temperature - 40 to 85 o c t j junction temperature - 40 to 125 o c note 3: r efer to the typical application circuit . note 4: v drop defined as the v in - v out voltage at v out = 98% normal v out . the linear regulator must provide the output mosfet with sufficient gate - to - source voltage (v gs = v cc - v out ) to regulate the output voltage. e l e c t r i c a l c h a r a c t e r i s t i c s unless otherwise specified, these specifications apply over v cc = 5/12v, t a = - 40 to 85 o c. typical values are at t a =25 o c. ap l5610/a/b/c symbol parameter test conditions min . typ . max . unit supply current v cc = 12v - 0.8 1.0 i cc vcc supply current v cc = 5v - 0.8 1.0 ma v cc = 12v, en=gnd - - 5 i sd vcc shutdown current v cc = 5v, en=gnd - - 5 m a power - on - reset (por) vcc por threshold v cc rising 3.8 4.0 4.2 v vcc por hysteresis - 0.4 - v reference voltage apl5610/a - 0.8 - v v ref reference voltage v cc = 12v, t a = 2 5 o c apl5610b/c - 0.5 - v reference vo ltage accuracy v cc = 12v, t a = 2 5 o c - 0.5 - 0.5 % line regulation v cc = 4.5v to 13.2v - 1.5 - 1.5 % fb input current - 100 - 100 na error amplifier unity gain bandwidth v cc = 5/12v - 2 - mhz open loop dc gain v cc =12v, no load 60 80 - db psrr powe r supply rejection ratio v cc =12v, 100hz, no load 50 - - db v cc =12v, i drv (source) = 5 m a, v fb = 0.6v 11.2 11.5 - v drv (high) drv high voltage v cc =5v, i drv (source) = 5 m a, v fb = 0.6v - 4.7 - v v cc =12v, i drv (sink) = 5 m a, v fb = 1 v - 0.5 1 v drv (low) drv low voltage v cc =5v, i drv (sink) = 5 m a, v fb = 1 v - 0.8 - v v cc =12v, v drv = 6v, v fb = 0.6v - 50 - i drv (source) drv source current v cc =5v, v drv = 2.5v, v fb = 0.6v - 10 - ma v cc =12v, v drv = 6v, v fb = 1v - 40 - i drv (sink) drv sink current v cc =5v, v drv = 2.5v, v fb = 1v - 10 - ma c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) unless otherwise specified, these specifications apply over v cc = 5/12v, t a = - 40 to 85 o c. typical values are at t a =25 o c. ap l5610/a/b/c symbol parameter test conditions min . typ . max . unit enable v en (th) en logic high threshold voltage v en rising - 0.8 - v en hysteresis - 50 - mv en shutdown debounce v en falling - 2 - m s soft - start t ss soft - start interval 100 200 300 m s under - voltage protection (uvp) v uv (th) under - voltage threshold v en =5v, v fb falling 68 75 82 % uvp debounce interval - 5 - m s power - ok and delay v pok (th) rising pok threshold voltage v cc =12v, v fb rising - 90 - % pok threshold hysteresis v cc =12v - 15 - % pok pull - low voltage v cc =12v, pok sinks 4 ma - 0.2 0.4 v pok debounce interval v fb c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 6 o p e r a t i n g w a v e f o r m s t h e t e s t c o n d i t i o n t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . t u r n o n r e s p o n s e ch1: v cc , 2v/div, dc time: 2m s/div v cc =5v, v in =5v, v out =1.5v , c in =33 m f/ electrolytic,c out =1 m f/electrolytic, ch2: v drv , 2v/div, dc ch3: v out , 1v/div, dc ch4: v pok , 5v/div, dc t u r n o f f r e s p o n s e 1 2 v cc v out v pok 4 3 v drv ch1: v cc , 2v/div, dc time: 0.1s/div ch2: v drv , 2v/div, dc ch3: v out , 1v/div, dc ch4: v pok , 5v/div, dc v cc =5v, v in =5v, v out =1.5v , c in =33 m f/ electrolytic,c out =1 m f/electrolytic, l o a d t r a n s i e n t r e s p o n s e - 1 i load 1 2 v out time:100 m s/div v cc =5v, v in =5v, v out =1.5v, i load =0-5-0a(rising/falling edge=1a/ m s ), c in =22 m f/mlcc, c out =22 m f/mlcc, ch1: v out , 50mv/div, ac ch2: i out , 2a/div, dc 1 2 i load v out l o a d t r a n s i e n t r e s p o n s e - 2 1 2 4 3 v cc v out v pok v drv time:20 m s/div v cc =5v, v in =5v, v out =1.2v, i load =0-5-0a(rising/falling edge=1a/ m s ), c in =22 m f/mlcc, c out =100 m f/electrolytic, ch1: v out , 50mv/div, ac ch2: i out , 2a/div, dc c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 7 o p e r a t i n g w a v e f o r m s ( c o n t . ) t h e t e s t c o n d i t i o n t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . l o a d t r a n s i e n t r e s p o n s e - 3 v out 1 2 i out time:100 m s/div v cc =5v, v in =5v, v out =1.5v, i load =0-0.2-0a(rising/falling edge=1a/ m s ), c in =22 m f/mlcc, c out =22 m f/mlcc, ch1: v out , 20mv/div, ac ch2: i out , 100ma/div, dc s h o r t c i r c u i t r e s p o n s e ( s h o r t - c i r c u i t a f t e r p o w e r - u p ) 1 2 3 4 i out v out v pok v drv ch1: i out , 20a/div, dc time: 20 m s/div v cc =5v, v in =5v, v out =1.5v, c in =22 m f/mlcc,c out =22 m f/mlcc, ch2: v drv , 2v/div, dc ch3: v out (short to gnd after power-up),1v/div, dc ch4: v pok , 5v/div, dc s h o r t c i r c u i t r e s p o n s e ( s h o r t - c i r c u i t b e f o r e p o w e r - u p ) ch2: i out , 20a/div, dc time: 20 m s/div v cc =5v, v in =5v, v out =1.5v, c in =22 m f/mlcc,c out =22 m f/mlcc, ch1: v cc , 2v/div, dc ch4: v pok , 5v/div, dc ch3: v out (short to gnd before power-up),1v/div, dc 4 1 2 3 v ocb v out i out v cc v out v pok i out ( a p l 5 6 1 0 a ) c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 8 pin no. name function 1 en enable control pin. pulling the en high (v en > 1.6 ) enables the v out ; forcing the en low (v en <0. 4 v) disables the v out . when re - enabled, the ic undergoes a new soft - start process . 2 gnd ground pin of the circuitry. all voltage l evels are measured with respect to this pin. 3 fb voltage feedback pin. connecting this pin to an external resistor divider receives the feedback voltage of the regulator. 4 pok power - ok signal output pin. this pin is an open - drain output used to indicat e the status of output voltage by sensing fb voltage. this pin is pulled low when output voltage is not within the power - ok voltage window. 5 drv this pin drives the gate of an external n - channel mosfet for linear regulator . 6 vcc power input pin of the device. the voltage at this pin is monitored for power - on - reset purpose. p i n d e s c r i p t i o n b l o c k d i a g r a m fb 75%v ref en vcc drv gnd pok delay enable_ea pwok internal regulator uvp comparator control logic 90%v ref 0.8v v ref 0.8v enable e n a b l e _ e a p o r power-on reset soft- start power-ok comparator error amplifier uv c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 9 t y p i c a l a p p l i c a t i o n c i r c u i t v cc 5v or 12v v in 1.5v en drv gnd apl5610 apl5610a apl5610b apl5610c pok fb v out 1.2v c out 100 m f c in 100 m f r1 10k w r2 20k w vcc c cc 1 m f on off en pok r3 100k w apm4354kp c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 1 0 f u n c t i o n d e s c r i p t i o n power-on-reset (por) the apl5610 series monitors the vcc pin voltage (v cc ) for power-on-reset function to prevent wrong operation. the built-in por circuit keeps the output shutting off until internal circuit is operating properly. typical por thresh- old is 4.0v with 0.4v hysteresis. soft-start the apl5610 series provides an internal soft-start cir- cuitry to control rise rate of the output voltage and limit the current surge during start-up. typical soft-start interval is about 0.3ms. under-voltage protection (uvp) the apl5610 series monitors the voltage on fb. when the voltage on fb falls below the under-voltage threshold, the uvp circuit shuts off the output voltage immediately by pulling down drv to 0v and latches apl5610 series off, requiring either a v cc por or en re-enable again to restart. enable control t h e a p l 5 6 1 0 series h a s a d e d i c a t e d e n a b l e p i n ( e n ) . a l o g i c l o w s i g n a l a p p l i e d t o t h i s p i n s h u t s d o w n t h e o u t p u t . f o l l o w i n g a s h u t d o w n , a l o g i c h i g h s i g n a l r e - e n a b l e s t h e o u t p u t t h r o u g h i n i t i a t i o n o f a n e w s o f t - s t a r t c y c l e . i t ? s n o t n e c e s s a r y t o u s e a n e x t e r n a l t r a n s i s t o r t o s a v e c o s t . power-ok and delay the apl5610 series indicates the status of the output voltage by monitoring the feedback voltage (v fb ) on fb pin. as the v fb rises and reaches the rising power-ok voltage threshold (v pokth ), an internal delay function starts to work. at the end of the delay time, the ic turns off the internal nmos of the pok to indicate that the output is ok. as the v fb falls and reaches the falling power-ok voltage threshold, the ic turns on the nmos of the pok (after a debounce time of 5 m s typical). output voltage regulation the a p l 5 6 1 0 series is a linear regulator controller. an external n-channel mosfet should be connected to drv as the pass element. the output voltage set by the resis- tor divider is determined by: ? ? ? ? ? + = ? ? ? ? ? + = 2 r 1 r 1 x 5 . 0 v 2 r 1 r 1 x 8 . 0 v out out where r1 is connected from vout to fb and r2 is con- nected from fb to gnd. t h e u v p a c t i v a t i o n t i m i n g i s d i f f e r e n t i n t h e s e 4 v a r i a n t s o f i c , t h e a p l 5 6 1 0 , a p l 5 6 1 0 a , a p l 5 6 1 0 b , a p l 5 6 1 0 c . t h e a p l 5 6 1 0 a n d a p l 5 6 1 0 b u v p i s a c t i v a t e d a f t e r v o u t v o l t - a g e h a s r e a c h e d 9 0 % p o k t h r e s h o l d w h i l e t h e a p l 5 6 1 0 a a n d a p l 5 6 1 0 c u v p i s a c t i v a t e d a f t e r v c c h a s b e e n a p - p l i e d t o v c c p i n . i n o r d e r t o a v o i d e r r o n e o u s u v p l a t c h - o f f i n a p l 5 6 1 0 a a n d a p l 5 6 1 0 c , p l e a s e m a k e s u r e t h e p o w e r s e q u e n c e i s a p r o p e r o n e w h e n y o u u s e t h e a p l 5 6 1 0 a a n d a p l 5 6 1 0 c . f o r t h e s u g g e s t e d p o w e r s e - q u e n c e o f a p l 5 6 1 0 a a n d a p l 5 6 1 0 c , y o u c a n r e f e r t o t h e p o w e r s e q u e n c i n g i n a p p l i c a t i o n i n f o r m a t i o n . for apl5610, apl5610a for apl5610b, apl5610c c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 1 1 a p p l i c a t i o n i n f o r m a t i o n i n p u t c a p a c i t o r the apl5610 series requires proper input capacitor of v in (connected to the external mosfet?s drain) to supply surge current during stepping load transients to prevent the input rail from dropping. because the parasitic induc- tor from the voltage sources or other bulk capacitors to the v in limits the slew rate of the surge current, it is nec- essary to place the input capacitor near the mosfet?s drain as close as possible. if the mosfet is located near the bulk capacitor for upstream voltage regulator, this input capacitor may not be required. the input ca- pacitor for v in should be larger than 1 m f. higher capaci- tance of this v in input capacitor is needed if the stepping load transients are large and fast. a n o t h e r i n p u t c a p a c i t o r f o r v c c i s r e c o m m e n d e d . p l a c i n g t h e i n p u t c a p a c i t o r o f v c c a s c l o s e t o v c c p i n a s p o s s i b l e p r e v e n t s o u t s i d e n o i s e f r o m e n t e r i n g a p l 5 6 1 0 ? s c o n t r o l c i r c u i t r y . t h e r e c o m m e n d e d c a p a c i t a n c e o f v c c i n p u t c a p a c i t o r i s 1 m f . o u t p u t c a p a c i t o r the apl5610 series needs a proper output capacitor to maintain circuit stability and to improve transient response over temperature and current. in order to insure the cir- cuit stability, the proper output capacitor value should be larger than 10 m f. with x5r and x7r dielectrics, 22 m f is sufficient at all operating temperatures. p o k p u l l h i g h the pok is an open-drain output that needs to be pulled high to a proper voltage (not greater than 5.5v) via a pull- up resistor. the pull-up resistor can be 20k w ~100k w . m o s f e t s e l e c t i o n apl5610 series r e q u i r e s a n n - c h a n n e l m o s f e t a s a p a s s e l e m e n t . t h e r e a r e s o m e p a r a m e t e r s m u s t b e c o n - s i d e r e d i n s e l e c t i n g a m o f s e t , i n c l u d i n g : t h r e s h o l d v o l t - a g e v t h , r d s ( o n ) , c o n t i n u o u s i d s c u r r e n t a n d p a c k a g e t h e r - m a l r e s i s t a n c e . t h e m o s f e t s e l e c t i o n g u i d e l i n e s a r e l i s t e d a s b e l o w : 1 . t h r e s h o l d v o l t a g e v t h : s e l e c t t h e m o s f e t v t h r a t i n g t o m e e t t h e f o l l o w i n g e q u a t i o n : v t h < v c c ( m i n ) ? v o u t ( m a x ) 2 . r ds(on) : select the mosfet r ds(on) to ensure that the output voltage will never enter dropout: r ds(on )(max) < (v in(min) ?v out(max) )/ i out(max) (note: r ds(on)(max) must be met at all temperatures and at the minimum v gs condition) 3 . c o n t i n u o u s i d s ( m a x ) : s e l e c t t h e i d s ( m a x ) t h a t c a n s u p p o r t t h e o u t p u t c u r r e n t : c o n t i n u o u s i d s ( m a x ) > i o u t ( m a x ) 4 . package thermal resistance q (ja) : select a package of mosfet that can dissipate the heat, q (ja) < (t j ?t a )/p d , where t j is the maximum allowable junction tempera- ture of mosfet, t a is the ambient temperature, p d is the maximum power dissipation on mosfet, calculated as below: p d =(v in(max) ?v out(min) ) x i out(max) p o w e r s e q u e n c i n g ( o n l y f o r a p l 5 6 1 0 a a n d a p l 5 6 1 0 c ) a t s t a r t - u p , i t i s n e c e s s a r y t o e n s u r e t h a t t h e v i n ( t h e v o l t - a g e s u p p l i e d t o m o s f e t d r a i n ) , v c c a n d v e n a r e s e - q u e n c e d c o r r e c t l y t o a v o i d e r r o n e o u s l a t c h - o f f . t o a v o i d u v p l a t c h - o f f h a p p e n e d a t s t a r t - u p d u e t o s e q u e n c i n g i s s u e s , t h e k e y m e t h o d i s t h e v i n s h o u l d b e l a r g e r t h a n t h e o u t p u t u n d e r - v o l t a g e t h r e s h o l d p l u s t h e d r o p t h r o u g h t h e p a s s m o s f e t w h e n t h a t o u t p u t i s e n a b l e d . figure 1 and 2 show the two types of power on sequence. figure 1 shows the v cc comes up before the v in , and then the output would be enabled when the v en is applied. figure 2 shows the v in comes up before the v cc , and then the output can either be enabled with the v cc or v en . rec- ommended power on sequence is shown in figure1 and 2. f i g u r e 1 . a p l 5 6 1 0 a / c s u p p l y c o m e s u p b e f o r e m o s f e t d r a i n s u p p l y v cc v in v en v out v en(th) v uv(th) v en(th) occurs after v uv(th) is reached c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 1 2 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) layout consideration f i g u r e 3 i l l u s t r a t e s t h e l a y o u t . b e l o w i s a c h e c k l i s t f o r y o u r l a y o u t : 1 . p l e a s e p l a c e t h e i n p u t c a p a c i t o r c v c c c l o s e t o t h e v c c p i n . 2 . p l e a s e p l a c e t h e c v i n c l o s e t o t h e m o s f e t ? s d r a i n . 3 . l a y o u t a c o p p e r p l a n e f o r n - c h a n n e l m o s f e t ? s d r a i n t o i m p r o v e t h e h e a t d i s s i p a t i o n . 4 . o u t p u t c a p a c i t o r c o u t f o r l o a d m u s t b e p l a c e d n e a r t h e l o a d a s c l o s e a s p o s s i b l e . . f i g u r e 3 p o w e r s e q u e n c i n g ( o n l y f o r a p l 5 6 1 0 a a n d a p l 5 6 1 0 c ) ( c o n t . ) f i g u r e 2 . m o s f e t d r a i n s u p p l y c o m e s u p b e f o r e a p l 5 6 1 0 a / c s u p p l y short-circuit concerns (only for apl5610 and apl5610b) v cc v in v en v out v en(th) v uv(th) v en(th) occurs after v uv(th) is reached since the apl5610 and apl5610b uvp function is acti- vated after the v out reaches 90% level, any combinations of sequence among v in , v cc , and v en are allowable. however, please note that the advantage of none-power- sequencing brings a drawback. if and only if a short-cir- cuit condition of output voltage occurs before v in supply, the uvp won?t be activated. thus, the short-circuit current persists to flow and could impair the mosfet. if in your application the short-circuit is most likely to be encoun- tered before v in supply, we suggest you use the apl5610a or apl5610c instead of the apl5610 or apl5610b, who can provide this short-circuit protection. nevertheless, if the v in supply can provide the ocp protection, this short- circuit won?t be an issue in apl5610. 2 . 2 0 1 . 2 7 0.65 0.95 1.90 unit : mm s o t - 2 3 - 6 f i g u r e 4 . r e c o m m e n d e d m i n i m u m f o o t p r i n t 5 . l a r g e c u r r e n t p a t h s , t h e b o l d l i n e s i n f i g u r e 3 , m u s t h a v e w i d e t r a c k s . c vcc v in vcc drv fb c out apl5610 apl5610a apl5610b apl5610c gnd v cc c vin r 1 r2 load c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 1 3 p a c k a g e i n f o r m a t i o n s o t - 2 3 - 6 0 l view a 0 . 2 5 gauge plane seating plane a a 2 a 1 e d e 1 see view a b c e1 e 0 8 0 8 0.020 0.009 0.006 0.024 0.051 0.057 max. 0.30 l 0 e e e1 e1 d c b 0.08 0.30 0.012 0.60 0.95 bsc 1.90 bsc 0.50 0.22 0.075 bsc 0.037 bsc 0.012 0.003 millimeters min. s y m b o l a1 a2 a 0.00 0.90 sot-23-6 max. 1.30 0.15 1.45 min. 0.000 0.035 inches 1.40 2.60 3.00 1.80 2.70 3.10 0.118 0.071 0.122 0.102 0.055 0.106 note : 1. follow jedec to-178 ab. 2. dimension d and e1 do not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 10 mil per side. seating plane < 4 mils -t- c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 1 4 application a h t1 c d d w e1 f 178.0 ? 2.00 50 min. 8.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 8.0 ? 0.30 1.75 ? 0.10 3.5 ? 0.05 p0 p1 p2 d0 d1 t a0 b0 k0 sot - 23 - 6 4.0 ? 0.10 4.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.0 min. 0.6+0.00 - 0.4 0 3.20 ? 0.20 3.10 ? 0.20 1.50 ? 0.20 (mm) d e v i c e s p e r u n i t c a r r i e r t a p e & r e e l d i m e n s i o n s package type unit quantity sot - 23 - 6 tape & reel 3000 a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 1 5 t a p i n g d i r e c t i o n i n f o r m a t i o n s o t - 2 3 - 6 c l a s s i f i c a t i o n p r o f i l e user direction of feed aaax aaax aaax aaax aaax aaax aaax c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 1 6 profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. c l a s s i f i c a t i o n r e f l o w p r o f i l e s table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c r e l i a b i l i t y t e s t p r o g r a m test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ t j =125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 7 - m a y . , 2 0 1 1 a p l 5 6 1 0 / a / b / c w w w . a n p e c . c o m . t w 1 7 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8 |
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